a. Field of the Invention
The present invention generally relates to semiconductor devices, and more particularly to structures, fabrication methods, and design structures having selective facetted epitaxial growth.
b. Background of Invention
In semiconductor structures, the epitaxial growth of regions such the source/drain (S/D) regions within Field Effect Transistors (FETs) may encounter faceting. In some instances, the created facets associated with these S/D epitaxially grown regions are desired, while in other instances, such facets may lead to undesirable effects.
Referring to FIG. 1A, within area A of semiconductor structure 100, the effect of epitaxially growing a raised S/D region 102 at the edge of an isolation region 104 (e.g., an STI region), as known in the art, is illustrated. This effect is shown in more detail in FIG. 1B, which depicts an expanded view of area A. Referring to FIG. 1B, the epitaxially grown raised S/D region 102 includes facets 106a-106c, which are formed at the edge of isolation region 104. Such faceting at the isolation region 104 edge is a known phenomenon associated epitaxial processes and is formed due to the crystalline growth (epitaxy) nature associated with the directional growth properties encountered at different surface atom concentrations.
Thus, growing the raised source/drain region 102 at the edge of isolation region 104 may cause the formation of facets 106a-106c. Facets 106a-106c along the edge of isolation region 104 are undesirable because the formed facets have less epitaxial material, which may lead to the entire epitaxial material associated with the facets being consumed during silicide formation. This reduces the contact area of the raised source/drain region 102 and, therefore, increases contact resistance with the raised source/drain region 102.
FIG. 2 depicts a cross sectional view of a semiconductor structure 200 that illustrates the effect of epitaxially growing raised S/D regions 202, 204, 206 at the edge of shallow trench isolation (STI) regions 208 and 210, as known in the art. As illustrated, facet 212 of raised S/D region 202 is formed at the edge of STI region 208. Similarly, facets 214 and 216 of raised S/D regions 204 and 206, respectively, are formed at the edge of STI region 210. As described above, facets associated with epitaxial raised S/D regions that are grown at the edge of STI regions may exhibit significantly reduced contact surface areas.
As shown in FIG. 2, raised S/D region 202 has a reduced contact surface area Sf1 relative to the contact surface area provided by S/D region 220. Likewise, raised S/D regions 204 and 206 have significantly reduced contact surface areas Sf2 and Sf3 compared to the contact surface area provided by S/D region 220. In the illustrated structure 220, since the STI regions 208, 210 are formed on an extremely thin silicon-on-insulator (ETSOI) layer 222 located on a buried oxide (BOX) layer 224, the shallow STI regions 208, 210 facilitate the formation of pronounced facets such as facets 212-216.
It may, therefore, be advantageous, among other things, to control the formation of facets during the growth of epitaxial regions within semiconductor structures.